1. Field of the Invention
The present invention relates to a buffer circuit for temporarily storing information transferred between computers, for example.
2. Description of Related Art
FIG. 12 is a circuit diagram showing a conventional buffer circuit. In FIG. 12, the reference numeral 1 designates an input terminal for inputting an input signal; 2 designates an input terminal for inputting EL disable signal (low (L) active signal) when halting the output of an output signal from an output terminal 11; reference numerals 3 and 4 each designate an inverter for inverting a signal level; 5 designates a NAND circuit to which the input signal and the inverted signal from the inverter 4 are supplied; 6 designates a NOR circuit to which the input signal and the inverted signal from the inverter 3 are supplied; 7 designates a power supply; 8 designates a ground; 9 designates a P-channel transistor that is brought out of conduction when its gate potential is at a high (H) level, and into conduction when its gate potential is at a low (L) level; 10 designates an N-channel transistor that is brought into conduction when its gate potential is at a high (H) level, and out of conduction when its gate potential is at a low (L) level; and 11 designates the output terminal for outputting an output signal.
Next, the operation of the conventional buffer circuit will be described.
The buffer circuit of FIG. 12 outputs from the output terminal 11 an L level signal when an L level input signal is supplied to the input terminal 1, and an H level signal when an H level input signal is supplied to the input terminal 1. Let us assume here that the disable signal to the input terminal 2 is always placed at the H level so as to enable the output signal to be output from the output terminal 11, because only the operation of this case will be described here.
First, when the L level input signal is supplied to the input terminal 1, the NAND circuit 5 is supplied with the L level input signal and the H level inverted signal as shown in FIG. 13, placing the gate potential of the P-channel transistor 9 at the H level. Accordingly, the P-channel transistor 9 is brought out of conduction, and the output terminal 11 is disconnected from the power supply 7.
At the same time, when the L level input signal is supplied to the input terminal 1, the NOR circuit 6 is supplied with the L level input signal and the L level inverted signal as shown in FIG. 13, placing the gate potential of the N-channel transistor 10 at the H level. Accordingly, the N-channel transistor 10 is brought into conduction, and the output terminal 11 is connected to the ground 8.
Thus, when the L level signal is input to the input terminal 1, the output terminal 11 is connected to the ground 8, which will place the potential of the output terminal 11 at zero, thereby producing the L level output signal from the output terminal 11.
Second, when the H level input signal is supplied to the input terminal 1, the NAND circuit 5 is supplied with the H level input signal and the H level inverted signal as shown in FIG. 14, placing the gate potential of the P-channel transistor 9 at the L level. Accordingly, the P-channel transistor 9 is brought into conduction, and the output terminal 11 is connected to the power supply 7.
At the same time, when the H level input signal is supplied to the input terminal 1, the NOR circuit 6 is supplied with the H level input signal and the L level inverted signal as shown in FIG. 14, placing the gate potential of the N-channel transistor 10 at the L level. Accordingly, the N-channel transistor 10 is brought out of conduction, and the output terminal 11 is disconnected from the ground 8.
Thus, when the H level signal is input to the input terminal 1, the output terminal 11 is connected to the power supply 7. This will place the potential of the output terminal 11 at the power supply level, thereby producing the H level output signal from the output terminal 11.
Therefore, when the input signal rises from the L level to H level, the output signal also changes from the L level to H level. In this case, the voltage rising rate of the output signal is determined by the capacity of a load connected to the output terminal 11 and the on-resistance of the P-channel transistor 9. An increase of the capacity of the load connected to the output terminal 11 will reduce the voltage rising rate, thereby increasing a delay time between the rise of the input signal to the H level and that of the output signal to the H level.
With the foregoing arrangement, the conventional buffer circuit can produce the output signal of the same level as the input signal. The buffer circuit, however, has a problem of an increasing delay time between the rise of the input signal and that of the output signal due to an increase of the capacity of the load connected to the output terminal 11.